1. Field of the Invention
The present invention relates to control of continuous data reading in a semiconductor memory device and more particularly to a semiconductor memory device which performs data output control and judgment of output data validity when suspend and resume functions are used during continuous data reading, and a method of controlling the same.
2. Description of Related Art
Conventionally, in semiconductor memory devices, continuous data reading operation (burst mode, etc) has been performed in order to transmit data to a system controller (processor, etc) through a system bus at high speed. In this type of system, plural devices including a semiconductor memory device are connected with the system bus and an individual device occupies the system bus for data access and is switched to another device as necessary. When a semiconductor memory device is reading data continuously while occupying the system bus, it may become necessary for the device to surrender the system bus to another device temporarily upon a request from the system controller, etc. In order to cope with such a situation, the semiconductor memory device has a suspend function, a function of stopping continuous reading operation temporarily.
Some suspend functions are performed by stopping supply of external clock signals to stop internal circuit operation. However, for system operation, it is not desirable to stop clock signals to be supplied to the whole system, in order to perform the suspend function of the semiconductor memory device.
In a burst mode flash memory disclosed in Japanese unexamined patent publication No. 2001-176277, paragraphs 0016, 0017, 0063 and 0066, FIGS. 1 and 12, an output enable buffer 210 receives an external output enable signal 210a as shown in FIG. 9. The external output enable signal 210a is sent by a processor through a system bus. In response to the external output enable signal 210a, the output enable buffer 210 generates an internal output enable signal 210b. The internal output enable signal 210b is sent to a burst suspend part 121. In the burst suspend part 121, a clock enable signal COEB is outputted to a clock buffer 300. The clock buffer 300 controls a buffer clock signal CLKB which is synchronized with an external clock signal CLKESDR in response to the clock enable signal COEB. During continuous data reading in which a buffer clock signal CLKB is to be generated to enable internal operation, the supply of a buffer clock signal CLKB is stopped and data output is prohibited or disabled in the suspend mode.
The internal output enable signal 210b is also sent to an output buffer 190. As shown in FIG. 10, in the output buffer 190, a latch 607a which receives read data (Data) is connected with one input of a NOR gate 609a and one input of a NAND gate 611a. The other input of the NOR gate 609a is connected with the internal output enable signal 210b. The other input of the NAND gate 611a is connected with an inverter 603b which receives the internal output enable signal 210b as an input. The data is outputted through an output signal OUT when the internal output enable signal 210b is “low.”
On the other hand, in the burst mode flash memory disclosed by Japanese unexamined patent publication No. 2001-176277, while a system controller (not shown) acquires data from a system bus (not shown) in synchronization with an external clock signal CLKESDR, data output from the output buffer 190 which is stopped by a suspend function is performed according to the internal output enable signal 210b asynchronously with the external clock signal CLKESD. When the external output enable signal 210a is inputted asynchronously with the external clock signal CLKESDR, the time of prohibition of data output from the output buffer 190 fluctuates before or after the next cycle of the external clock signal CLKESDR depending on the time of transition of the external output enable signal 210a. The problem here is that the time of prohibition of output data upon entry into the suspend mode cannot be uniquely determined.
In order to determine the time of prohibition uniquely, data output must be prohibited before start of the next cycle even if transition of the external output enable signal 210a is delayed until the setup time of the external clock signal CLKESDR. The setup time must be longer than the internal circuit delay time from transition of the external output enable signal 210a until prohibition of output data. This would put a limit on shortening of the external clock signal CLKESDR cycle, making it impossible to cope with high speed operation.
Also, for effective use of the system bus, it is desirable that switching between devices which access data be quickly done and the system controller should quickly detect that the system bus has become open (unoccupied). However, Japanese unexamined patent publication No. 2001-176277 does not disclose a notification signal which notifies that the suspend mode is entered through an external output enable signal 210a from the system controller and data output is prohibited. The problem here is that the system controller cannot detect the time of suspend mode entry through the external output enable signal 210a and may fail to allocate the system bus, which is opened, to another device quickly.
In addition, if switching is done too early, output data may still be not prohibited. If that should be the case, a bus fight might occur and reliability of data might not be assured.